From 0935ff50e2cf186fbff2095fcfed8e2d8ae2843f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 4 Sep 2024 02:10:48 +0100 Subject: [PATCH 1/4] wip(py2): Update vexriscv to support py2hwsw --- iob_vexriscv.py | 202 ++++++++++++++++++++++++++++++++++-------------- 1 file changed, 144 insertions(+), 58 deletions(-) diff --git a/iob_vexriscv.py b/iob_vexriscv.py index e4b6535..7637fd2 100644 --- a/iob_vexriscv.py +++ b/iob_vexriscv.py @@ -1,59 +1,145 @@ -#!/usr/bin/env python3 +def setup(py_params_dict): + attributes_dict = { + "original_name": "iob_vexriscv", + "name": "iob_vexriscv", + "version": "0.1", + "generate_hw": False, + "confs": [ + { + "name": "ADDR_W", + "type": "P", + "val": "32", + "min": "1", + "max": "?", + "descr": "description here", + }, + { + "name": "DATA_W", + "type": "P", + "val": "32", + "min": "1", + "max": "?", + "descr": "description here", + }, + { + "name": "E_BIT", + "type": "P", + "val": "67", + "min": "1", + "max": "?", + "descr": "description here", + }, + { + "name": "P_BIT", + "type": "P", + "val": "66", + "min": "1", + "max": "?", + "descr": "description here", + }, + { + "name": "USE_EXTMEM", + "type": "P", + "val": "0", + "min": "0", + "max": "1", + "descr": "Select if configured for usage with external memory.", + }, + ], + "ports": [ + { + "name": "clk_en_rst", + "descr": "Clock, clock enable and reset", + "interface": { + "type": "clk_en_rst", + "subtype": "slave", + }, + }, + { + "name": "rst", + "descr": "Synchronous reset", + "signals": [ + { + "name": "rst", + "direction": "input", + "width": "1", + "descr": "CPU synchronous reset", + }, + # TODO: Deprecate boot input. Instead update reset address to 0x80000000. + # { + # "name": "boot", + # "direction": "input", + # "width": "1", + # "descr": "CPU boot mode", + # }, + ], + }, + # TODO: Deprecate REQ and RESP + # { + # "name": "instruction_bus", + # "descr": "Instruction bus", + # "signals": [ + # { + # "name": "ibus_req", + # "direction": "output", + # "n_bits": "`REQ_W", + # "descr": "Instruction bus request", + # }, + # { + # "name": "ibus_resp", + # "direction": "input", + # "n_bits": "`RESP_W", + # "descr": "Instruction bus response", + # }, + # ], + # }, + # { + # "name": "data_bus", + # "descr": "Data bus", + # "signals": [ + # { + # "name": "dbus_req", + # "direction": "output", + # "n_bits": "`REQ_W", + # "descr": "Data bus request", + # }, + # { + # "name": "dbus_resp", + # "direction": "input", + # "n_bits": "`RESP_W", + # "descr": "Data bus response", + # }, + # ], + # }, + { + "name": "i_bus", + "descr": "iob-picorv32 instruction bus", + "interface": { + "type": "iob", + "subtype": "master", + "port_prefix": "ibus_", + "DATA_W": "DATA_W", + "ADDR_W": "ADDR_W", + }, + }, + { + "name": "d_bus", + "descr": "iob-picorv32 data bus", + "interface": { + "type": "iob", + "subtype": "master", + "port_prefix": "dbus_", + "DATA_W": "DATA_W", + "ADDR_W": "ADDR_W", + }, + }, + ], + "blocks": [ + { + "core_name": "iob_reg_re", + "instance_name": "iob_reg_re_inst", + }, + ], + } -import os -import sys -import shutil - -from iob_module import iob_module - -# Submodules -from iob_reg_re import iob_reg_re - -class iob_vexriscv(iob_module): - name = "iob_vexriscv" - version = "V0.10" - flows = "" - setup_dir=os.path.dirname(__file__) - - @classmethod - def _create_submodules_list(cls): - ''' Create submodules list with dependencies of this module - ''' - super()._create_submodules_list([ - iob_reg_re, - ]) - - @classmethod - def _setup_confs(cls): - super()._setup_confs([ - # Macros - - # Parameters - {'name':'ADDR_W', 'type':'P', 'val':'32', 'min':'1', 'max':'?', 'descr':'description here'}, - {'name':'DATA_W', 'type':'P', 'val':'32', 'min':'1', 'max':'?', 'descr':'description here'}, - {'name':'E_BIT', 'type':'P', 'val':'67', 'min':'1', 'max':'?', 'descr':'description here'}, - {'name':'P_BIT', 'type':'P', 'val':'66', 'min':'1', 'max':'?', 'descr':'description here'}, - {'name':'USE_EXTMEM', 'type':'P', 'val':'0', 'min':'0', 'max':'1', 'descr':'Select if configured for usage with external memory.'}, - ]) - - @classmethod - def _setup_ios(cls): - cls.ios += [ - {'name': 'general', 'descr':'General interface signals', 'ports': [ - {'name':"clk", 'type':"I", 'n_bits':'1', 'descr':"CPU clock input"}, - {'name':"rst", 'type':"I", 'n_bits':'1', 'descr':"CPU reset input"}, - {'name':"boot", 'type':"I", 'n_bits':'1', 'descr':"CPU boot input"}, - ]}, - {'name': 'instruction_bus', 'descr':'Instruction bus', 'ports': [ - {'name':"ibus_req", 'type':"O", 'n_bits':'`REQ_W', 'descr':"Instruction bus request"}, - {'name':"ibus_resp", 'type':"I", 'n_bits':'`RESP_W', 'descr':"Instruction bus response"}, - ]}, - {'name': 'data_bus', 'descr':'Data bus', 'ports': [ - {'name':"dbus_req", 'type':"O", 'n_bits':'`REQ_W', 'descr':"Data bus request"}, - {'name':"dbus_resp", 'type':"I", 'n_bits':'`RESP_W', 'descr':"Data bus response"}, - ]} - ] - - @classmethod - def _setup_block_groups(cls): - cls.block_groups += [] + return attributes_dict From 23363e58d32f3c86e3dd788edfe8215cbd5b8a06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 4 Sep 2024 20:50:36 +0100 Subject: [PATCH 2/4] feat(iob_vexriscv): Generate with py2hwsw; Remove req/resp and boot signals --- hardware/src/iob_VexRiscv.v | 341 ------------------------------------ iob_vexriscv.py | 284 ++++++++++++++++++++++++------ 2 files changed, 229 insertions(+), 396 deletions(-) delete mode 100644 hardware/src/iob_VexRiscv.v diff --git a/hardware/src/iob_VexRiscv.v b/hardware/src/iob_VexRiscv.v deleted file mode 100644 index aef750b..0000000 --- a/hardware/src/iob_VexRiscv.v +++ /dev/null @@ -1,341 +0,0 @@ -/* - * IOb-VexRiscv -- A VexRiscv Wrapper - */ -`timescale 1 ns / 1 ps -`include "iob_vexriscv_conf.vh" -`include "iob_utils.vh" - -module iob_VexRiscv #( - parameter IBUS_AXI_ID_W = 1, - parameter IBUS_AXI_LEN_W = 8, - parameter IBUS_AXI_ADDR_W = 32, - parameter IBUS_AXI_DATA_W = 32, - parameter DBUS_AXI_ID_W = 1, - parameter DBUS_AXI_LEN_W = 8, - parameter DBUS_AXI_ADDR_W = 32, - parameter DBUS_AXI_DATA_W = 32, - `include "iob_vexriscv_params.vs" -) ( - input wire clk_i, - input wire cke_i, - input wire arst_i, - input wire cpu_reset_i, - - // CLINT bus - input wire [ `REQ_W-1:0] clint_req, - output wire [`RESP_W-1:0] clint_resp, - - // PLIC bus - input wire [ `REQ_W-1:0] plic_req, - output wire [`RESP_W-1:0] plic_resp, - input wire [ 31:0] plicInterrupts, - - // Axi instruction bus - `include "iBus_axi_m_port.vs" - // Axi data bus - `include "dBus_axi_m_port.vs" - - input wire boot_i -); - - wire reset; - - wire clint_iob_valid; - wire [ ADDR_W-1:0] clint_iob_addr; - wire [ DATA_W-1:0] clint_iob_wdata; - wire [DATA_W/8-1:0] clint_iob_wstrb; - wire clint_iob_rvalid; - wire [ DATA_W-1:0] clint_iob_rdata; - wire clint_iob_ready; - - wire clint_awvalid; - wire clint_awready; - wire [ 15:0] clint_awaddr; - wire [ 2:0] clint_awprot; - wire clint_wvalid; - wire clint_wready; - wire [ 31:0] clint_wdata; - wire [ 3:0] clint_wstrb; - wire clint_bvalid; - wire clint_bready; - wire [ 1:0] clint_bresp; - wire clint_arvalid; - wire clint_arready; - wire [ 15:0] clint_araddr; - wire [ 2:0] clint_arprot; - wire clint_rvalid; - wire clint_rready; - wire [ 31:0] clint_rdata; - wire [ 1:0] clint_rresp; - - wire plic_iob_valid; - wire [ ADDR_W-1:0] plic_iob_addr; - wire [ DATA_W-1:0] plic_iob_wdata; - wire [DATA_W/8-1:0] plic_iob_wstrb; - wire plic_iob_rvalid; - wire [ DATA_W-1:0] plic_iob_rdata; - wire plic_iob_ready; - - wire plic_awvalid; - wire plic_awready; - wire [ 21:0] plic_awaddr; - wire [ 2:0] plic_awprot; - wire plic_wvalid; - wire plic_wready; - wire [ 31:0] plic_wdata; - wire [ 3:0] plic_wstrb; - wire plic_bvalid; - wire plic_bready; - wire [ 1:0] plic_bresp; - wire plic_arvalid; - wire plic_arready; - wire [ 21:0] plic_araddr; - wire [ 2:0] plic_arprot; - wire plic_rvalid; - wire plic_rready; - wire [ 31:0] plic_rdata; - wire [ 1:0] plic_rresp; - - wire [ DATA_W-1:0] iBus_axi_araddr_int; - wire [ 3:0] iBus_axi_arregion; - wire iBus_axi_arlock; - reg [ DATA_W-1:0] dBus_axi_awaddr; - wire [ DATA_W-1:0] dBus_axi_awaddr_int; - wire [ 3:0] dBus_axi_awregion; - wire dBus_axi_awlock; - reg [ DATA_W-1:0] dBus_axi_araddr; - wire [ DATA_W-1:0] dBus_axi_araddr_int; - wire [ 3:0] dBus_axi_arregion; - wire dBus_axi_arlock; - wire w_periphral_sel; - wire r_periphral_sel; - - assign reset = cpu_reset_i | arst_i; - - assign w_periphral_sel = &dBus_axi_awaddr_int[ADDR_W-1:ADDR_W-4]; - assign r_periphral_sel = &dBus_axi_araddr_int[ADDR_W-1:ADDR_W-4]; - - assign iBus_axi_awvalid_o = 1'b0; - assign iBus_axi_awaddr_o = {ADDR_W{1'b0}}; - assign iBus_axi_awid_o = 1'b0; - assign iBus_axi_awlen_o = {IBUS_AXI_LEN_W{1'b0}}; - assign iBus_axi_awsize_o = {3{1'b0}}; - assign iBus_axi_awburst_o = {2{1'b0}}; - assign iBus_axi_awlock_o = 1'b0; - assign iBus_axi_awcache_o = {4{1'b0}}; - assign iBus_axi_awqos_o = {4{1'b0}}; - assign iBus_axi_awprot_o = {3{1'b0}}; - assign iBus_axi_wvalid_o = 1'b0; - assign iBus_axi_wdata_o = {DATA_W{1'b0}}; - assign iBus_axi_wstrb_o = {DATA_W / 8{1'b0}}; - assign iBus_axi_wlast_o = 1'b0; - assign iBus_axi_bready_o = 1'b0; - assign iBus_axi_araddr_o = {boot_i, iBus_axi_araddr_int[ADDR_W-2:0]}; - assign iBus_axi_arlock_o = {1'b0, iBus_axi_arlock}; - - assign dBus_axi_awaddr_o = dBus_axi_awaddr; - assign dBus_axi_araddr_o = dBus_axi_araddr; - assign dBus_axi_awlock_o = {1'b0, dBus_axi_awlock}; - assign dBus_axi_arlock_o = {1'b0, dBus_axi_arlock}; - - always @(*) begin - if (w_periphral_sel) begin - dBus_axi_awaddr = dBus_axi_awaddr_int; - end else begin - dBus_axi_awaddr = { - boot_i & (~dBus_axi_awaddr_int[ADDR_W-1]), dBus_axi_awaddr_int[ADDR_W-2:0] - }; - end - end - - always @(*) begin - if (r_periphral_sel) begin - dBus_axi_araddr = dBus_axi_araddr_int; - end else begin - dBus_axi_araddr = { - boot_i & (~dBus_axi_araddr_int[ADDR_W-1]), dBus_axi_araddr_int[ADDR_W-2:0] - }; - end - end - - assign {plic_iob_valid, plic_iob_addr, plic_iob_wdata, plic_iob_wstrb} = plic_req; - assign plic_resp = {plic_iob_rdata, plic_iob_rvalid, plic_iob_ready}; - assign {clint_iob_valid, clint_iob_addr, clint_iob_wdata, clint_iob_wstrb} = clint_req; - assign clint_resp = {clint_iob_rdata, clint_iob_rvalid, clint_iob_ready}; - // instantiate iob2axil clint - iob2axil #( - .AXIL_ADDR_W(16), - .AXIL_DATA_W(32), - .ADDR_W(ADDR_W), - .DATA_W(DATA_W) - ) clint_iob2axil ( - // IOb-bus slave signals - .iob_valid_i(clint_iob_valid), - .iob_addr_i(clint_iob_addr), - .iob_wdata_i(clint_iob_wdata), - .iob_wstrb_i(clint_iob_wstrb), - .iob_rvalid_o(clint_iob_rvalid), - .iob_rdata_o(clint_iob_rdata), - .iob_ready_o(clint_iob_ready), - // AXIL master signals - .axil_awvalid_o(clint_awvalid), - .axil_awready_i(clint_awready), - .axil_awaddr_o(clint_awaddr), - .axil_awprot_o(clint_awprot), - .axil_wvalid_o(clint_wvalid), - .axil_wready_i(clint_wready), - .axil_wdata_o(clint_wdata), - .axil_wstrb_o(clint_wstrb), - .axil_bvalid_i(clint_bvalid), - .axil_bready_o(clint_bready), - .axil_bresp_i(clint_bresp), - .axil_arvalid_o(clint_arvalid), - .axil_arready_i(clint_arready), - .axil_araddr_o(clint_araddr), - .axil_arprot_o(clint_arprot), - .axil_rvalid_i(clint_rvalid), - .axil_rready_o(clint_rready), - .axil_rdata_i(clint_rdata), - .axil_rresp_i(clint_rresp) - ); - // instantiate iob2axil plic - iob2axil #( - .AXIL_ADDR_W(22), - .AXIL_DATA_W(32), - .ADDR_W(ADDR_W), - .DATA_W(DATA_W) - ) plic_iob2axil ( - // IOb-bus slave signals - .iob_valid_i(plic_iob_valid), - .iob_addr_i(plic_iob_addr), - .iob_wdata_i(plic_iob_wdata), - .iob_wstrb_i(plic_iob_wstrb), - .iob_rvalid_o(plic_iob_rvalid), - .iob_rdata_o(plic_iob_rdata), - .iob_ready_o(plic_iob_ready), - // AXIL master signals - .axil_awvalid_o(plic_awvalid), - .axil_awready_i(plic_awready), - .axil_awaddr_o(plic_awaddr), - .axil_awprot_o(plic_awprot), - .axil_wvalid_o(plic_wvalid), - .axil_wready_i(plic_wready), - .axil_wdata_o(plic_wdata), - .axil_wstrb_o(plic_wstrb), - .axil_bvalid_i(plic_bvalid), - .axil_bready_o(plic_bready), - .axil_bresp_i(plic_bresp), - .axil_arvalid_o(plic_arvalid), - .axil_arready_i(plic_arready), - .axil_araddr_o(plic_araddr), - .axil_arprot_o(plic_arprot), - .axil_rvalid_i(plic_rvalid), - .axil_rready_o(plic_rready), - .axil_rdata_i(plic_rdata), - .axil_rresp_i(plic_rresp) - ); - - // Instantiation of VexRiscvAxi4LinuxPlicClint - VexRiscvAxi4LinuxPlicClint CPU ( - .clint_awvalid(clint_awvalid), - .clint_awready(clint_awready), - .clint_awaddr(clint_awaddr), - .clint_awprot(clint_awprot), - .clint_wvalid(clint_wvalid), - .clint_wready(clint_wready), - .clint_wdata(clint_wdata), - .clint_wstrb(clint_wstrb), - .clint_bvalid(clint_bvalid), - .clint_bready(clint_bready), - .clint_bresp(clint_bresp), - .clint_arvalid(clint_arvalid), - .clint_arready(clint_arready), - .clint_araddr(clint_araddr), - .clint_arprot(clint_arprot), - .clint_rvalid(clint_rvalid), - .clint_rready(clint_rready), - .clint_rdata(clint_rdata), - .clint_rresp(clint_rresp), - .plic_awvalid(plic_awvalid), - .plic_awready(plic_awready), - .plic_awaddr(plic_awaddr), - .plic_awprot(plic_awprot), - .plic_wvalid(plic_wvalid), - .plic_wready(plic_wready), - .plic_wdata(plic_wdata), - .plic_wstrb(plic_wstrb), - .plic_bvalid(plic_bvalid), - .plic_bready(plic_bready), - .plic_bresp(plic_bresp), - .plic_arvalid(plic_arvalid), - .plic_arready(plic_arready), - .plic_araddr(plic_araddr), - .plic_arprot(plic_arprot), - .plic_rvalid(plic_rvalid), - .plic_rready(plic_rready), - .plic_rdata(plic_rdata), - .plic_rresp(plic_rresp), - .plicInterrupts(plicInterrupts), - .iBusAxi_arvalid(iBus_axi_arvalid_o), - .iBusAxi_arready(iBus_axi_arready_i), - .iBusAxi_araddr(iBus_axi_araddr_int), - .iBusAxi_arid(iBus_axi_arid_o), - .iBusAxi_arregion(iBus_axi_arregion), - .iBusAxi_arlen(iBus_axi_arlen_o), - .iBusAxi_arsize(iBus_axi_arsize_o), - .iBusAxi_arburst(iBus_axi_arburst_o), - .iBusAxi_arlock(iBus_axi_arlock), - .iBusAxi_arcache(iBus_axi_arcache_o), - .iBusAxi_arqos(iBus_axi_arqos_o), - .iBusAxi_arprot(iBus_axi_arprot_o), - .iBusAxi_rvalid(iBus_axi_rvalid_i), - .iBusAxi_rready(iBus_axi_rready_o), - .iBusAxi_rdata(iBus_axi_rdata_i), - .iBusAxi_rid(iBus_axi_rid_i), - .iBusAxi_rresp(iBus_axi_rresp_i), - .iBusAxi_rlast(iBus_axi_rlast_i), - .dBusAxi_awvalid(dBus_axi_awvalid_o), - .dBusAxi_awready(dBus_axi_awready_i), - .dBusAxi_awaddr(dBus_axi_awaddr_int), - .dBusAxi_awid(dBus_axi_awid_o), - .dBusAxi_awregion(dBus_axi_awregion), - .dBusAxi_awlen(dBus_axi_awlen_o), - .dBusAxi_awsize(dBus_axi_awsize_o), - .dBusAxi_awburst(dBus_axi_awburst_o), - .dBusAxi_awlock(dBus_axi_awlock), - .dBusAxi_awcache(dBus_axi_awcache_o), - .dBusAxi_awqos(dBus_axi_awqos_o), - .dBusAxi_awprot(dBus_axi_awprot_o), - .dBusAxi_wvalid(dBus_axi_wvalid_o), - .dBusAxi_wready(dBus_axi_wready_i), - .dBusAxi_wdata(dBus_axi_wdata_o), - .dBusAxi_wstrb(dBus_axi_wstrb_o), - .dBusAxi_wlast(dBus_axi_wlast_o), - .dBusAxi_bvalid(dBus_axi_bvalid_i), - .dBusAxi_bready(dBus_axi_bready_o), - .dBusAxi_bid(dBus_axi_bid_i), - .dBusAxi_bresp(dBus_axi_bresp_i), - .dBusAxi_arvalid(dBus_axi_arvalid_o), - .dBusAxi_arready(dBus_axi_arready_i), - .dBusAxi_araddr(dBus_axi_araddr_int), - .dBusAxi_arid(dBus_axi_arid_o), - .dBusAxi_arregion(dBus_axi_arregion), - .dBusAxi_arlen(dBus_axi_arlen_o), - .dBusAxi_arsize(dBus_axi_arsize_o), - .dBusAxi_arburst(dBus_axi_arburst_o), - .dBusAxi_arlock(dBus_axi_arlock), - .dBusAxi_arcache(dBus_axi_arcache_o), - .dBusAxi_arqos(dBus_axi_arqos_o), - .dBusAxi_arprot(dBus_axi_arprot_o), - .dBusAxi_rvalid(dBus_axi_rvalid_i), - .dBusAxi_rready(dBus_axi_rready_o), - .dBusAxi_rdata(dBus_axi_rdata_i), - .dBusAxi_rid(dBus_axi_rid_i), - .dBusAxi_rresp(dBus_axi_rresp_i), - .dBusAxi_rlast(dBus_axi_rlast_i), - .clk(clk_i), - .reset(reset) - ); - - -endmodule diff --git a/iob_vexriscv.py b/iob_vexriscv.py index 7637fd2..afc9539 100644 --- a/iob_vexriscv.py +++ b/iob_vexriscv.py @@ -3,7 +3,6 @@ def setup(py_params_dict): "original_name": "iob_vexriscv", "name": "iob_vexriscv", "version": "0.1", - "generate_hw": False, "confs": [ { "name": "ADDR_W", @@ -45,15 +44,44 @@ def setup(py_params_dict): "max": "1", "descr": "Select if configured for usage with external memory.", }, + { + "name": "AXI_ID_W", + "descr": "AXI ID bus width", + "type": "P", + "val": 0, + "min": "1", + "max": "32", + }, + { + "name": "AXI_ADDR_W", + "descr": "AXI address bus width", + "type": "P", + "val": 0, + "min": "1", + "max": "32", + }, + { + "name": "AXI_DATA_W", + "descr": "AXI data bus width", + "type": "P", + "val": 0, + "min": "1", + "max": "32", + }, + { + "name": "AXI_LEN_W", + "descr": "AXI burst length width", + "type": "P", + "val": 0, + "min": "1", + "max": "4", + }, ], "ports": [ { "name": "clk_en_rst", "descr": "Clock, clock enable and reset", - "interface": { - "type": "clk_en_rst", - "subtype": "slave", - }, + "interface": {"type": "clk_en_rst", "subtype": "slave"}, }, { "name": "rst", @@ -61,61 +89,17 @@ def setup(py_params_dict): "signals": [ { "name": "rst", + "descr": "CPU synchronous reset", "direction": "input", "width": "1", - "descr": "CPU synchronous reset", }, - # TODO: Deprecate boot input. Instead update reset address to 0x80000000. - # { - # "name": "boot", - # "direction": "input", - # "width": "1", - # "descr": "CPU boot mode", - # }, ], }, - # TODO: Deprecate REQ and RESP - # { - # "name": "instruction_bus", - # "descr": "Instruction bus", - # "signals": [ - # { - # "name": "ibus_req", - # "direction": "output", - # "n_bits": "`REQ_W", - # "descr": "Instruction bus request", - # }, - # { - # "name": "ibus_resp", - # "direction": "input", - # "n_bits": "`RESP_W", - # "descr": "Instruction bus response", - # }, - # ], - # }, - # { - # "name": "data_bus", - # "descr": "Data bus", - # "signals": [ - # { - # "name": "dbus_req", - # "direction": "output", - # "n_bits": "`REQ_W", - # "descr": "Data bus request", - # }, - # { - # "name": "dbus_resp", - # "direction": "input", - # "n_bits": "`RESP_W", - # "descr": "Data bus response", - # }, - # ], - # }, { "name": "i_bus", "descr": "iob-picorv32 instruction bus", "interface": { - "type": "iob", + "type": "axi", "subtype": "master", "port_prefix": "ibus_", "DATA_W": "DATA_W", @@ -126,19 +110,209 @@ def setup(py_params_dict): "name": "d_bus", "descr": "iob-picorv32 data bus", "interface": { - "type": "iob", + "type": "axi", "subtype": "master", "port_prefix": "dbus_", "DATA_W": "DATA_W", "ADDR_W": "ADDR_W", }, }, + { + "name": "clint_cbus", + "descr": "CLINT CSRs bus", + "interface": { + "type": "axi", + "subtype": "slave", + "port_prefix": "clint_", + "ID_W": "AXI_ID_W", + "ADDR_W": "AXI_ADDR_W", + "DATA_W": "AXI_DATA_W", + "LEN_W": "AXI_LEN_W", + }, + }, + { + "name": "plic_cbus", + "descr": "PLIC CSRs bus", + "interface": { + "type": "axi", + "subtype": "slave", + "port_prefix": "plic_", + "ID_W": "AXI_ID_W", + "ADDR_W": "AXI_ADDR_W", + "DATA_W": "AXI_DATA_W", + "LEN_W": "AXI_LEN_W", + }, + }, + { + "name": "plic_interrupts", + "descr": "PLIC interrupts", + "signals": [ + { + "name": "plic_interrupts", + "descr": "PLIC interrupts", + "direction": "input", + "width": "32", + }, + ], + }, ], - "blocks": [ + "wires": [ { - "core_name": "iob_reg_re", - "instance_name": "iob_reg_re_inst", + "name": "cpu_reset", + "descr": "cpu reset signal", + "signals": [ + {"name": "cpu_reset", "direction": "input", "width": "1"}, + ], }, + { + "name": "ibus_int", + "descr": "ibus internal signals", + "signals": [ + {"name": "iBus_axi_arregion", "width": "3"}, + {"name": "iBus_axi_arlock", "width": "1"}, + ], + }, + { + "name": "dbus_int", + "descr": "dbus internal signals", + "signals": [ + {"name": "dBus_axi_awregion", "width": "3"}, + {"name": "dBus_axi_awlock", "width": "1"}, + {"name": "dBus_axi_arregion", "width": "3"}, + {"name": "dBus_axi_arlock", "width": "1"}, + ], + }, + ], + "snippets": [ + { + "verilog_code": """ + // Instantiation of VexRiscv, Plic, and Clint + VexRiscvAxi4LinuxPlicClint CPU ( + .clint_awvalid(clint_awvalid), + .clint_awready(clint_awready), + .clint_awaddr(clint_awaddr), + .clint_awprot(clint_awprot), + .clint_wvalid(clint_wvalid), + .clint_wready(clint_wready), + .clint_wdata(clint_wdata), + .clint_wstrb(clint_wstrb), + .clint_bvalid(clint_bvalid), + .clint_bready(clint_bready), + .clint_bresp(clint_bresp), + .clint_arvalid(clint_arvalid), + .clint_arready(clint_arready), + .clint_araddr(clint_araddr), + .clint_arprot(clint_arprot), + .clint_rvalid(clint_rvalid), + .clint_rready(clint_rready), + .clint_rdata(clint_rdata), + .clint_rresp(clint_rresp), + .plic_awvalid(plic_awvalid), + .plic_awready(plic_awready), + .plic_awaddr(plic_awaddr), + .plic_awprot(plic_awprot), + .plic_wvalid(plic_wvalid), + .plic_wready(plic_wready), + .plic_wdata(plic_wdata), + .plic_wstrb(plic_wstrb), + .plic_bvalid(plic_bvalid), + .plic_bready(plic_bready), + .plic_bresp(plic_bresp), + .plic_arvalid(plic_arvalid), + .plic_arready(plic_arready), + .plic_araddr(plic_araddr), + .plic_arprot(plic_arprot), + .plic_rvalid(plic_rvalid), + .plic_rready(plic_rready), + .plic_rdata(plic_rdata), + .plic_rresp(plic_rresp), + .plicInterrupts(plicInterrupts), + .iBusAxi_arvalid(iBus_axi_arvalid_o), + .iBusAxi_arready(iBus_axi_arready_i), + .iBusAxi_araddr(iBus_axi_araddr_o), + .iBusAxi_arid(iBus_axi_arid_o), + .iBusAxi_arregion(iBus_axi_arregion), + .iBusAxi_arlen(iBus_axi_arlen_o), + .iBusAxi_arsize(iBus_axi_arsize_o), + .iBusAxi_arburst(iBus_axi_arburst_o), + .iBusAxi_arlock(iBus_axi_arlock), + .iBusAxi_arcache(iBus_axi_arcache_o), + .iBusAxi_arqos(iBus_axi_arqos_o), + .iBusAxi_arprot(iBus_axi_arprot_o), + .iBusAxi_rvalid(iBus_axi_rvalid_i), + .iBusAxi_rready(iBus_axi_rready_o), + .iBusAxi_rdata(iBus_axi_rdata_i), + .iBusAxi_rid(iBus_axi_rid_i), + .iBusAxi_rresp(iBus_axi_rresp_i), + .iBusAxi_rlast(iBus_axi_rlast_i), + .dBusAxi_awvalid(dBus_axi_awvalid_o), + .dBusAxi_awready(dBus_axi_awready_i), + .dBusAxi_awaddr(dBus_axi_awaddr_o), + .dBusAxi_awid(dBus_axi_awid_o), + .dBusAxi_awregion(dBus_axi_awregion), + .dBusAxi_awlen(dBus_axi_awlen_o), + .dBusAxi_awsize(dBus_axi_awsize_o), + .dBusAxi_awburst(dBus_axi_awburst_o), + .dBusAxi_awlock(dBus_axi_awlock), + .dBusAxi_awcache(dBus_axi_awcache_o), + .dBusAxi_awqos(dBus_axi_awqos_o), + .dBusAxi_awprot(dBus_axi_awprot_o), + .dBusAxi_wvalid(dBus_axi_wvalid_o), + .dBusAxi_wready(dBus_axi_wready_i), + .dBusAxi_wdata(dBus_axi_wdata_o), + .dBusAxi_wstrb(dBus_axi_wstrb_o), + .dBusAxi_wlast(dBus_axi_wlast_o), + .dBusAxi_bvalid(dBus_axi_bvalid_i), + .dBusAxi_bready(dBus_axi_bready_o), + .dBusAxi_bid(dBus_axi_bid_i), + .dBusAxi_bresp(dBus_axi_bresp_i), + .dBusAxi_arvalid(dBus_axi_arvalid_o), + .dBusAxi_arready(dBus_axi_arready_i), + .dBusAxi_araddr(dBus_axi_araddr_o), + .dBusAxi_arid(dBus_axi_arid_o), + .dBusAxi_arregion(dBus_axi_arregion), + .dBusAxi_arlen(dBus_axi_arlen_o), + .dBusAxi_arsize(dBus_axi_arsize_o), + .dBusAxi_arburst(dBus_axi_arburst_o), + .dBusAxi_arlock(dBus_axi_arlock), + .dBusAxi_arcache(dBus_axi_arcache_o), + .dBusAxi_arqos(dBus_axi_arqos_o), + .dBusAxi_arprot(dBus_axi_arprot_o), + .dBusAxi_rvalid(dBus_axi_rvalid_i), + .dBusAxi_rready(dBus_axi_rready_o), + .dBusAxi_rdata(dBus_axi_rdata_i), + .dBusAxi_rid(dBus_axi_rid_i), + .dBusAxi_rresp(dBus_axi_rresp_i), + .dBusAxi_rlast(dBus_axi_rlast_i), + .clk(clk_i), + .reset(cpu_reset) + ); + + + + assign cpu_reset = rst_i | arst_i; + + assign iBus_axi_awvalid_o = 1'b0; + assign iBus_axi_awaddr_o = {ADDR_W{1'b0}}; + assign iBus_axi_awid_o = 1'b0; + assign iBus_axi_awlen_o = {IBUS_AXI_LEN_W{1'b0}}; + assign iBus_axi_awsize_o = {3{1'b0}}; + assign iBus_axi_awburst_o = {2{1'b0}}; + assign iBus_axi_awlock_o = 1'b0; + assign iBus_axi_awcache_o = {4{1'b0}}; + assign iBus_axi_awqos_o = {4{1'b0}}; + assign iBus_axi_awprot_o = {3{1'b0}}; + assign iBus_axi_wvalid_o = 1'b0; + assign iBus_axi_wdata_o = {DATA_W{1'b0}}; + assign iBus_axi_wstrb_o = {DATA_W / 8{1'b0}}; + assign iBus_axi_wlast_o = 1'b0; + assign iBus_axi_bready_o = 1'b0; + assign iBus_axi_arlock_o = {1'b0, iBus_axi_arlock}; + + assign dBus_axi_awlock_o = {1'b0, dBus_axi_awlock}; + assign dBus_axi_arlock_o = {1'b0, dBus_axi_arlock}; +""" + } ], } From dc1971cf07a99e1776042a382b778f3c7f449ddb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Thu, 5 Sep 2024 18:32:59 +0100 Subject: [PATCH 3/4] fix(vexriscv): Add axi2axil converters; Fix signal names and widths; Remove unused parameters. --- iob_vexriscv.py | 361 ++++++++++++++++++++++++++---------------------- 1 file changed, 195 insertions(+), 166 deletions(-) diff --git a/iob_vexriscv.py b/iob_vexriscv.py index afc9539..0dab4b5 100644 --- a/iob_vexriscv.py +++ b/iob_vexriscv.py @@ -4,46 +4,6 @@ def setup(py_params_dict): "name": "iob_vexriscv", "version": "0.1", "confs": [ - { - "name": "ADDR_W", - "type": "P", - "val": "32", - "min": "1", - "max": "?", - "descr": "description here", - }, - { - "name": "DATA_W", - "type": "P", - "val": "32", - "min": "1", - "max": "?", - "descr": "description here", - }, - { - "name": "E_BIT", - "type": "P", - "val": "67", - "min": "1", - "max": "?", - "descr": "description here", - }, - { - "name": "P_BIT", - "type": "P", - "val": "66", - "min": "1", - "max": "?", - "descr": "description here", - }, - { - "name": "USE_EXTMEM", - "type": "P", - "val": "0", - "min": "0", - "max": "1", - "descr": "Select if configured for usage with external memory.", - }, { "name": "AXI_ID_W", "descr": "AXI ID bus width", @@ -102,8 +62,11 @@ def setup(py_params_dict): "type": "axi", "subtype": "master", "port_prefix": "ibus_", - "DATA_W": "DATA_W", - "ADDR_W": "ADDR_W", + "ID_W": "AXI_ID_W", + "ADDR_W": "AXI_ADDR_W", + "DATA_W": "AXI_DATA_W", + "LEN_W": "AXI_LEN_W", + "LOCK_W": 1, }, }, { @@ -113,8 +76,11 @@ def setup(py_params_dict): "type": "axi", "subtype": "master", "port_prefix": "dbus_", - "DATA_W": "DATA_W", - "ADDR_W": "ADDR_W", + "ID_W": "AXI_ID_W", + "ADDR_W": "AXI_ADDR_W", + "DATA_W": "AXI_DATA_W", + "LEN_W": "AXI_LEN_W", + "LOCK_W": 1, }, }, { @@ -125,7 +91,7 @@ def setup(py_params_dict): "subtype": "slave", "port_prefix": "clint_", "ID_W": "AXI_ID_W", - "ADDR_W": "AXI_ADDR_W", + "ADDR_W": "16", "DATA_W": "AXI_DATA_W", "LEN_W": "AXI_LEN_W", }, @@ -138,7 +104,7 @@ def setup(py_params_dict): "subtype": "slave", "port_prefix": "plic_", "ID_W": "AXI_ID_W", - "ADDR_W": "AXI_ADDR_W", + "ADDR_W": "22", "DATA_W": "AXI_DATA_W", "LEN_W": "AXI_LEN_W", }, @@ -168,122 +134,185 @@ def setup(py_params_dict): "name": "ibus_int", "descr": "ibus internal signals", "signals": [ - {"name": "iBus_axi_arregion", "width": "3"}, - {"name": "iBus_axi_arlock", "width": "1"}, + {"name": "ibus_axi_arregion_int", "width": "4"}, + {"name": "ibus_axi_arlock_int", "width": "1"}, ], }, { "name": "dbus_int", "descr": "dbus internal signals", "signals": [ - {"name": "dBus_axi_awregion", "width": "3"}, - {"name": "dBus_axi_awlock", "width": "1"}, - {"name": "dBus_axi_arregion", "width": "3"}, - {"name": "dBus_axi_arlock", "width": "1"}, + {"name": "dbus_axi_awregion_int", "width": "4"}, + {"name": "dbus_axi_awlock_int", "width": "1"}, + {"name": "dbus_axi_arregion_int", "width": "4"}, + {"name": "dbus_axi_arlock_int", "width": "1"}, ], }, + { + "name": "clint_cbus_axil", + "descr": "CLINT CSRs bus", + "interface": { + "type": "axil", + "subtype": "slave", + "wire_prefix": "clint_", + "ID_W": "AXI_ID_W", + "ADDR_W": "16", + "DATA_W": "AXI_DATA_W", + "LEN_W": "AXI_LEN_W", + }, + }, + { + "name": "plic_cbus_axil", + "descr": "PLIC CSRs bus", + "interface": { + "type": "axil", + "subtype": "slave", + "wire_prefix": "plic_", + "ID_W": "AXI_ID_W", + "ADDR_W": "22", + "DATA_W": "AXI_DATA_W", + "LEN_W": "AXI_LEN_W", + }, + }, + ], + "blocks": [ + { + "core_name": "axi2axil", + "instance_name": "clint_axi2axil", + "instance_description": "Convert AXI to AXI lite for CLINT", + "parameters": { + "AXI_ID_W": "AXI_ID_W", + "AXI_ADDR_W": "16", + "AXI_DATA_W": "AXI_DATA_W", + "AXI_LEN_W": "AXI_LEN_W", + }, + "connect": { + "axi": "clint_cbus", + "axil": "clint_cbus_axil", + }, + }, + { + "core_name": "axi2axil", + "instance_name": "plic_axi2axil", + "instance_description": "Convert AXI to AXI lite for PLIC", + "parameters": { + "AXI_ID_W": "AXI_ID_W", + "AXI_ADDR_W": "22", + "AXI_DATA_W": "AXI_DATA_W", + "AXI_LEN_W": "AXI_LEN_W", + }, + "connect": { + "axi": "plic_cbus", + "axil": "plic_cbus_axil", + }, + }, ], "snippets": [ { "verilog_code": """ // Instantiation of VexRiscv, Plic, and Clint VexRiscvAxi4LinuxPlicClint CPU ( - .clint_awvalid(clint_awvalid), - .clint_awready(clint_awready), - .clint_awaddr(clint_awaddr), - .clint_awprot(clint_awprot), - .clint_wvalid(clint_wvalid), - .clint_wready(clint_wready), - .clint_wdata(clint_wdata), - .clint_wstrb(clint_wstrb), - .clint_bvalid(clint_bvalid), - .clint_bready(clint_bready), - .clint_bresp(clint_bresp), - .clint_arvalid(clint_arvalid), - .clint_arready(clint_arready), - .clint_araddr(clint_araddr), - .clint_arprot(clint_arprot), - .clint_rvalid(clint_rvalid), - .clint_rready(clint_rready), - .clint_rdata(clint_rdata), - .clint_rresp(clint_rresp), - .plic_awvalid(plic_awvalid), - .plic_awready(plic_awready), - .plic_awaddr(plic_awaddr), - .plic_awprot(plic_awprot), - .plic_wvalid(plic_wvalid), - .plic_wready(plic_wready), - .plic_wdata(plic_wdata), - .plic_wstrb(plic_wstrb), - .plic_bvalid(plic_bvalid), - .plic_bready(plic_bready), - .plic_bresp(plic_bresp), - .plic_arvalid(plic_arvalid), - .plic_arready(plic_arready), - .plic_araddr(plic_araddr), - .plic_arprot(plic_arprot), - .plic_rvalid(plic_rvalid), - .plic_rready(plic_rready), - .plic_rdata(plic_rdata), - .plic_rresp(plic_rresp), - .plicInterrupts(plicInterrupts), - .iBusAxi_arvalid(iBus_axi_arvalid_o), - .iBusAxi_arready(iBus_axi_arready_i), - .iBusAxi_araddr(iBus_axi_araddr_o), - .iBusAxi_arid(iBus_axi_arid_o), - .iBusAxi_arregion(iBus_axi_arregion), - .iBusAxi_arlen(iBus_axi_arlen_o), - .iBusAxi_arsize(iBus_axi_arsize_o), - .iBusAxi_arburst(iBus_axi_arburst_o), - .iBusAxi_arlock(iBus_axi_arlock), - .iBusAxi_arcache(iBus_axi_arcache_o), - .iBusAxi_arqos(iBus_axi_arqos_o), - .iBusAxi_arprot(iBus_axi_arprot_o), - .iBusAxi_rvalid(iBus_axi_rvalid_i), - .iBusAxi_rready(iBus_axi_rready_o), - .iBusAxi_rdata(iBus_axi_rdata_i), - .iBusAxi_rid(iBus_axi_rid_i), - .iBusAxi_rresp(iBus_axi_rresp_i), - .iBusAxi_rlast(iBus_axi_rlast_i), - .dBusAxi_awvalid(dBus_axi_awvalid_o), - .dBusAxi_awready(dBus_axi_awready_i), - .dBusAxi_awaddr(dBus_axi_awaddr_o), - .dBusAxi_awid(dBus_axi_awid_o), - .dBusAxi_awregion(dBus_axi_awregion), - .dBusAxi_awlen(dBus_axi_awlen_o), - .dBusAxi_awsize(dBus_axi_awsize_o), - .dBusAxi_awburst(dBus_axi_awburst_o), - .dBusAxi_awlock(dBus_axi_awlock), - .dBusAxi_awcache(dBus_axi_awcache_o), - .dBusAxi_awqos(dBus_axi_awqos_o), - .dBusAxi_awprot(dBus_axi_awprot_o), - .dBusAxi_wvalid(dBus_axi_wvalid_o), - .dBusAxi_wready(dBus_axi_wready_i), - .dBusAxi_wdata(dBus_axi_wdata_o), - .dBusAxi_wstrb(dBus_axi_wstrb_o), - .dBusAxi_wlast(dBus_axi_wlast_o), - .dBusAxi_bvalid(dBus_axi_bvalid_i), - .dBusAxi_bready(dBus_axi_bready_o), - .dBusAxi_bid(dBus_axi_bid_i), - .dBusAxi_bresp(dBus_axi_bresp_i), - .dBusAxi_arvalid(dBus_axi_arvalid_o), - .dBusAxi_arready(dBus_axi_arready_i), - .dBusAxi_araddr(dBus_axi_araddr_o), - .dBusAxi_arid(dBus_axi_arid_o), - .dBusAxi_arregion(dBus_axi_arregion), - .dBusAxi_arlen(dBus_axi_arlen_o), - .dBusAxi_arsize(dBus_axi_arsize_o), - .dBusAxi_arburst(dBus_axi_arburst_o), - .dBusAxi_arlock(dBus_axi_arlock), - .dBusAxi_arcache(dBus_axi_arcache_o), - .dBusAxi_arqos(dBus_axi_arqos_o), - .dBusAxi_arprot(dBus_axi_arprot_o), - .dBusAxi_rvalid(dBus_axi_rvalid_i), - .dBusAxi_rready(dBus_axi_rready_o), - .dBusAxi_rdata(dBus_axi_rdata_i), - .dBusAxi_rid(dBus_axi_rid_i), - .dBusAxi_rresp(dBus_axi_rresp_i), - .dBusAxi_rlast(dBus_axi_rlast_i), + // CLINT + .clint_awvalid(clint_axil_awvalid), + .clint_awready(clint_axil_awready), + .clint_awaddr(clint_axil_awaddr), + .clint_awprot(clint_axil_awprot), + .clint_wvalid(clint_axil_wvalid), + .clint_wready(clint_axil_wready), + .clint_wdata(clint_axil_wdata), + .clint_wstrb(clint_axil_wstrb), + .clint_bvalid(clint_axil_bvalid), + .clint_bready(clint_axil_bready), + .clint_bresp(clint_axil_bresp), + .clint_arvalid(clint_axil_arvalid), + .clint_arready(clint_axil_arready), + .clint_araddr(clint_axil_araddr), + .clint_arprot(clint_axil_arprot), + .clint_rvalid(clint_axil_rvalid), + .clint_rready(clint_axil_rready), + .clint_rdata(clint_axil_rdata), + .clint_rresp(clint_axil_rresp), + // PLIC + .plic_awvalid(plic_axil_awvalid), + .plic_awready(plic_axil_awready), + .plic_awaddr(plic_axil_awaddr), + .plic_awprot(plic_axil_awprot), + .plic_wvalid(plic_axil_wvalid), + .plic_wready(plic_axil_wready), + .plic_wdata(plic_axil_wdata), + .plic_wstrb(plic_axil_wstrb), + .plic_bvalid(plic_axil_bvalid), + .plic_bready(plic_axil_bready), + .plic_bresp(plic_axil_bresp), + .plic_arvalid(plic_axil_arvalid), + .plic_arready(plic_axil_arready), + .plic_araddr(plic_axil_araddr), + .plic_arprot(plic_axil_arprot), + .plic_rvalid(plic_axil_rvalid), + .plic_rready(plic_axil_rready), + .plic_rdata(plic_axil_rdata), + .plic_rresp(plic_axil_rresp), + .plicInterrupts(plic_interrupts_i), + // Instruction Bus + .iBusAxi_arvalid(ibus_axi_arvalid_o), + .iBusAxi_arready(ibus_axi_arready_i), + .iBusAxi_araddr(ibus_axi_araddr_o), + .iBusAxi_arid(ibus_axi_arid_o), + .iBusAxi_arregion(ibus_axi_arregion_int), + .iBusAxi_arlen(ibus_axi_arlen_o), + .iBusAxi_arsize(ibus_axi_arsize_o), + .iBusAxi_arburst(ibus_axi_arburst_o), + .iBusAxi_arlock(ibus_axi_arlock_int), + .iBusAxi_arcache(ibus_axi_arcache_o), + .iBusAxi_arqos(ibus_axi_arqos_o), + .iBusAxi_arprot(ibus_axi_arprot_o), + .iBusAxi_rvalid(ibus_axi_rvalid_i), + .iBusAxi_rready(ibus_axi_rready_o), + .iBusAxi_rdata(ibus_axi_rdata_i), + .iBusAxi_rid(ibus_axi_rid_i), + .iBusAxi_rresp(ibus_axi_rresp_i), + .iBusAxi_rlast(ibus_axi_rlast_i), + // Data Bus + .dBusAxi_awvalid(dbus_axi_awvalid_o), + .dBusAxi_awready(dbus_axi_awready_i), + .dBusAxi_awaddr(dbus_axi_awaddr_o), + .dBusAxi_awid(dbus_axi_awid_o), + .dBusAxi_awregion(dbus_axi_awregion_int), + .dBusAxi_awlen(dbus_axi_awlen_o), + .dBusAxi_awsize(dbus_axi_awsize_o), + .dBusAxi_awburst(dbus_axi_awburst_o), + .dBusAxi_awlock(dbus_axi_awlock_int), + .dBusAxi_awcache(dbus_axi_awcache_o), + .dBusAxi_awqos(dbus_axi_awqos_o), + .dBusAxi_awprot(dbus_axi_awprot_o), + .dBusAxi_wvalid(dbus_axi_wvalid_o), + .dBusAxi_wready(dbus_axi_wready_i), + .dBusAxi_wdata(dbus_axi_wdata_o), + .dBusAxi_wstrb(dbus_axi_wstrb_o), + .dBusAxi_wlast(dbus_axi_wlast_o), + .dBusAxi_bvalid(dbus_axi_bvalid_i), + .dBusAxi_bready(dbus_axi_bready_o), + .dBusAxi_bid(dbus_axi_bid_i), + .dBusAxi_bresp(dbus_axi_bresp_i), + .dBusAxi_arvalid(dbus_axi_arvalid_o), + .dBusAxi_arready(dbus_axi_arready_i), + .dBusAxi_araddr(dbus_axi_araddr_o), + .dBusAxi_arid(dbus_axi_arid_o), + .dBusAxi_arregion(dbus_axi_arregion_int), + .dBusAxi_arlen(dbus_axi_arlen_o), + .dBusAxi_arsize(dbus_axi_arsize_o), + .dBusAxi_arburst(dbus_axi_arburst_o), + .dBusAxi_arlock(dbus_axi_arlock_int), + .dBusAxi_arcache(dbus_axi_arcache_o), + .dBusAxi_arqos(dbus_axi_arqos_o), + .dBusAxi_arprot(dbus_axi_arprot_o), + .dBusAxi_rvalid(dbus_axi_rvalid_i), + .dBusAxi_rready(dbus_axi_rready_o), + .dBusAxi_rdata(dbus_axi_rdata_i), + .dBusAxi_rid(dbus_axi_rid_i), + .dBusAxi_rresp(dbus_axi_rresp_i), + .dBusAxi_rlast(dbus_axi_rlast_i), + // Clock and Reset .clk(clk_i), .reset(cpu_reset) ); @@ -292,25 +321,25 @@ def setup(py_params_dict): assign cpu_reset = rst_i | arst_i; - assign iBus_axi_awvalid_o = 1'b0; - assign iBus_axi_awaddr_o = {ADDR_W{1'b0}}; - assign iBus_axi_awid_o = 1'b0; - assign iBus_axi_awlen_o = {IBUS_AXI_LEN_W{1'b0}}; - assign iBus_axi_awsize_o = {3{1'b0}}; - assign iBus_axi_awburst_o = {2{1'b0}}; - assign iBus_axi_awlock_o = 1'b0; - assign iBus_axi_awcache_o = {4{1'b0}}; - assign iBus_axi_awqos_o = {4{1'b0}}; - assign iBus_axi_awprot_o = {3{1'b0}}; - assign iBus_axi_wvalid_o = 1'b0; - assign iBus_axi_wdata_o = {DATA_W{1'b0}}; - assign iBus_axi_wstrb_o = {DATA_W / 8{1'b0}}; - assign iBus_axi_wlast_o = 1'b0; - assign iBus_axi_bready_o = 1'b0; - assign iBus_axi_arlock_o = {1'b0, iBus_axi_arlock}; + assign ibus_axi_awvalid_o = 1'b0; + assign ibus_axi_awaddr_o = {AXI_ADDR_W{1'b0}}; + assign ibus_axi_awid_o = 1'b0; + assign ibus_axi_awlen_o = {AXI_LEN_W{1'b0}}; + assign ibus_axi_awsize_o = {3{1'b0}}; + assign ibus_axi_awburst_o = {2{1'b0}}; + assign ibus_axi_awlock_o = 1'b0; + assign ibus_axi_awcache_o = {4{1'b0}}; + assign ibus_axi_awqos_o = {4{1'b0}}; + assign ibus_axi_awprot_o = {3{1'b0}}; + assign ibus_axi_wvalid_o = 1'b0; + assign ibus_axi_wdata_o = {AXI_DATA_W{1'b0}}; + assign ibus_axi_wstrb_o = {AXI_DATA_W / 8{1'b0}}; + assign ibus_axi_wlast_o = 1'b0; + assign ibus_axi_bready_o = 1'b0; + assign ibus_axi_arlock_o = {1'b0, ibus_axi_arlock_int}; - assign dBus_axi_awlock_o = {1'b0, dBus_axi_awlock}; - assign dBus_axi_arlock_o = {1'b0, dBus_axi_arlock}; + assign dbus_axi_awlock_o = {1'b0, dbus_axi_awlock_int}; + assign dbus_axi_arlock_o = {1'b0, dbus_axi_arlock_int}; """ } ], From cd04902c3eba2426117140d61c0805151ccd190a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Tue, 10 Sep 2024 00:41:22 +0100 Subject: [PATCH 4/4] feat(cache): Update uncached address range to match iob-soc peripherals. --- default.nix | 3 ++- hardware/src/VexRiscvAxi4LinuxPlicClint.v | 5 ++--- hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) mode change 120000 => 100644 default.nix diff --git a/default.nix b/default.nix deleted file mode 120000 index d306516..0000000 --- a/default.nix +++ /dev/null @@ -1 +0,0 @@ -submodules/LIB/scripts/default.nix \ No newline at end of file diff --git a/default.nix b/default.nix new file mode 100644 index 0000000..4785bd6 --- /dev/null +++ b/default.nix @@ -0,0 +1,2 @@ +{ pkgs ? import {} }: +import ../../lib/scripts/default.nix { inherit pkgs; } diff --git a/hardware/src/VexRiscvAxi4LinuxPlicClint.v b/hardware/src/VexRiscvAxi4LinuxPlicClint.v index d65aa4b..358d609 100644 --- a/hardware/src/VexRiscvAxi4LinuxPlicClint.v +++ b/hardware/src/VexRiscvAxi4LinuxPlicClint.v @@ -1,6 +1,5 @@ // Generator : SpinalHDL v1.9.3 git head : 029104c77a54c53f1edda327a3bea333f7d65fd9 // Component : VexRiscvAxi4LinuxPlicClint -// Git hash : 5ef1bc775fdbe942875dd7906f22aa98e6cffaaf `timescale 1ns/1ps @@ -4875,7 +4874,7 @@ module VexRiscvAxi4LinuxPlicClint ( end end - assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111); + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31] == 1'b1); assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockup); assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHits[0]; assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_1_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_1_virtualAddress[11 : 0]}; @@ -4995,7 +4994,7 @@ module VexRiscvAxi4LinuxPlicClint ( end end - assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111); + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31] == 1'b1); assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockup); assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHits[0]; assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_1_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_1_virtualAddress[11 : 0]}; diff --git a/hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala b/hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala index cf946d7..724a9c8 100644 --- a/hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala +++ b/hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala @@ -63,7 +63,7 @@ object VexRiscvAxi4LinuxPlicClint{ ) ), new MmuPlugin( - ioRange = _(31 downto 28) === 0xF + ioRange = _(31) === True ), new DecoderSimplePlugin( catchIllegalInstruction = true