diff --git a/default.nix b/default.nix
deleted file mode 120000
index d306516..0000000
--- a/default.nix
+++ /dev/null
@@ -1 +0,0 @@
-submodules/LIB/scripts/default.nix
\ No newline at end of file
diff --git a/default.nix b/default.nix
new file mode 100644
index 0000000..4785bd6
--- /dev/null
+++ b/default.nix
@@ -0,0 +1,2 @@
+{ pkgs ? import <nixpkgs> {} }:
+import ../../lib/scripts/default.nix { inherit pkgs; }
diff --git a/hardware/src/VexRiscvAxi4LinuxPlicClint.v b/hardware/src/VexRiscvAxi4LinuxPlicClint.v
index d65aa4b..358d609 100644
--- a/hardware/src/VexRiscvAxi4LinuxPlicClint.v
+++ b/hardware/src/VexRiscvAxi4LinuxPlicClint.v
@@ -1,6 +1,5 @@
 // Generator : SpinalHDL v1.9.3    git head : 029104c77a54c53f1edda327a3bea333f7d65fd9
 // Component : VexRiscvAxi4LinuxPlicClint
-// Git hash  : 5ef1bc775fdbe942875dd7906f22aa98e6cffaaf
 
 `timescale 1ns/1ps
 
@@ -4875,7 +4874,7 @@ module VexRiscvAxi4LinuxPlicClint (
     end
   end
 
-  assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111);
+  assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31] == 1'b1);
   assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockup);
   assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHits[0];
   assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_1_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_1_virtualAddress[11 : 0]};
@@ -4995,7 +4994,7 @@ module VexRiscvAxi4LinuxPlicClint (
     end
   end
 
-  assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111);
+  assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31] == 1'b1);
   assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockup);
   assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHits[0];
   assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_1_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_1_virtualAddress[11 : 0]};
diff --git a/hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala b/hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala
index cf946d7..724a9c8 100644
--- a/hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala
+++ b/hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala
@@ -63,7 +63,7 @@ object VexRiscvAxi4LinuxPlicClint{
             )
           ),
           new MmuPlugin(
-            ioRange      = _(31 downto 28) === 0xF
+            ioRange = _(31) === True
           ),
           new DecoderSimplePlugin(
             catchIllegalInstruction = true