info.yaml

# Tiny Tapeout project information
project:
  title:        "Multifunctional_signal_generator"      # Project title
  author:       "Electronic Cats"      # Your name
  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "Wave generator with ADSR"      # One line description of what your project does
  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
  clock_hz:     25000000       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_waves"

  # List your project's source files here.
  # Source files must be in ./src and you must list each source file separately, one per line.
  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
  source_files:
    - "tt_um_waves.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "uart_rx"
  ui[1]: ""
  ui[2]: ""
  ui[3]: ""
  ui[4]: ""
  ui[5]: ""
  ui[6]: ""
  ui[7]: ""

  # Outputs
  uo[0]: "sck"
  uo[1]: "ws"
  uo[2]: "sd"
  uo[3]: ""
  uo[4]: ""
  uo[5]: ""
  uo[6]: ""
  uo[7]: ""

  # Bidirectional pins
  uio[0]: "encoder_a_attack"
  uio[1]: "encoder_b_attack"
  uio[2]: "encoder_a_decay"
  uio[3]: "encoder_b_decay"
  uio[4]: "encoder_a_sustain"
  uio[5]: "encoder_b_sustain"
  uio[6]: "encoder_a_release"
  uio[7]: "encoder_b_release"

# Do not change!
yaml_version: 6