lab8.map.smsg

Info (10281): Verilog HDL Declaration information at level_state.sv(4): object "success" differs only in case from object "SUCCESS" in the same scope File: G:/intelFPGA/lab8/level_state.sv Line: 4
Info (10281): Verilog HDL Declaration information at level_state.sv(4): object "fail" differs only in case from object "FAIL" in the same scope File: G:/intelFPGA/lab8/level_state.sv Line: 4
Info (10281): Verilog HDL Declaration information at ISDU.sv(4): object "state" differs only in case from object "State" in the same scope File: G:/intelFPGA/lab8/ISDU.sv Line: 4
Info (10281): Verilog HDL Declaration information at key_control.sv(5): object "left" differs only in case from object "LEFT" in the same scope File: G:/intelFPGA/lab8/key_control.sv Line: 5
Info (10281): Verilog HDL Declaration information at key_control.sv(5): object "attack" differs only in case from object "ATTACK" in the same scope File: G:/intelFPGA/lab8/key_control.sv Line: 5
Info (10281): Verilog HDL Declaration information at key_control.sv(5): object "thump" differs only in case from object "THUMP" in the same scope File: G:/intelFPGA/lab8/key_control.sv Line: 5
Info (10281): Verilog HDL Declaration information at lab8_soc_mm_interconnect_0_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: G:/intelFPGA/lab8/lab8_soc/synthesis/submodules/lab8_soc_mm_interconnect_0_router_003.sv Line: 48
Info (10281): Verilog HDL Declaration information at lab8_soc_mm_interconnect_0_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: G:/intelFPGA/lab8/lab8_soc/synthesis/submodules/lab8_soc_mm_interconnect_0_router_003.sv Line: 49
Info (10281): Verilog HDL Declaration information at lab8_soc_mm_interconnect_0_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: G:/intelFPGA/lab8/lab8_soc/synthesis/submodules/lab8_soc_mm_interconnect_0_router_002.sv Line: 48
Info (10281): Verilog HDL Declaration information at lab8_soc_mm_interconnect_0_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: G:/intelFPGA/lab8/lab8_soc/synthesis/submodules/lab8_soc_mm_interconnect_0_router_002.sv Line: 49
Info (10281): Verilog HDL Declaration information at lab8_soc_mm_interconnect_0_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: G:/intelFPGA/lab8/lab8_soc/synthesis/submodules/lab8_soc_mm_interconnect_0_router_001.sv Line: 48
Info (10281): Verilog HDL Declaration information at lab8_soc_mm_interconnect_0_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: G:/intelFPGA/lab8/lab8_soc/synthesis/submodules/lab8_soc_mm_interconnect_0_router_001.sv Line: 49
Info (10281): Verilog HDL Declaration information at lab8_soc_mm_interconnect_0_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: G:/intelFPGA/lab8/lab8_soc/synthesis/submodules/lab8_soc_mm_interconnect_0_router.sv Line: 48
Info (10281): Verilog HDL Declaration information at lab8_soc_mm_interconnect_0_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: G:/intelFPGA/lab8/lab8_soc/synthesis/submodules/lab8_soc_mm_interconnect_0_router.sv Line: 49
Warning (10273): Verilog HDL warning at lab8.sv(320): extended using "x" or "z" File: G:/intelFPGA/lab8/lab8.sv Line: 320
Info (10281): Verilog HDL Declaration information at lab8.sv(45): object "LB" differs only in case from object "lb" in the same scope File: G:/intelFPGA/lab8/lab8.sv Line: 45
Warning (10273): Verilog HDL warning at HexDriver.sv(23): extended using "x" or "z" File: G:/intelFPGA/lab8/HexDriver.sv Line: 23
Info (10281): Verilog HDL Declaration information at enemy.sv(9): object "beida" differs only in case from object "BEIDA" in the same scope File: G:/intelFPGA/lab8/enemy.sv Line: 9
Info (10281): Verilog HDL Declaration information at enemy.sv(30): object "back" differs only in case from object "BACK" in the same scope File: G:/intelFPGA/lab8/enemy.sv Line: 30
Info (10281): Verilog HDL Declaration information at Little_Boss.sv(11): object "da" differs only in case from object "DA" in the same scope File: G:/intelFPGA/lab8/Little_Boss.sv Line: 11