question about pythia-HDL

[menglinhan]

Hello pythia owner

When I analyze the chisel code of pythia-HDL, I find the logic of code is different from the thesis(Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning). For example, sigQuery will change the state machine from idle to s_query_read2, the action only can be generated at the state of s_query_read16 and another sigQuery should be asserted in this state. Does this mean that it takes at least two requests to produce a prefetched action? Or the pythia-HDL can't implement the functions of pythia prefetch?

Thanks
BR
Menglin

[rahulbera]

Hi @menglinhan , the current Chisel code is merely used to get a rough estimate of Pythia's overhead. While I have tested this implementation with a few test cases, I believe it might not model a correct state machine for every possible states. So I would recommend to make the changes as you feel necessary for the correct operation. I would be more than happy to upstream your changes to the main repo with properly citing your contributions! :)

[menglinhan]

Hi @rahulbera , Thanks for your reply, I get your mean.

Here I have another confuse about the pc.
1) we must use load/store pc?
2) which stage pc should we use? retired now? excuting now? or prediction l/s pc? or the load/store pc which generate access to l2cache (Assume that the current pythia prefetcher object is l2). Or don't care what stage(due to different cpu has different implementation about pc)?

[rahulbera]

@menglinhan, it's the PC of the load instruction that generates the access to L2 cache. Note that: Pythia doesn't need to be invoked for store requests (neither writebacks from L1D, nor for read for ownership requests).

[rahulbera]

I am moving this issue to the Q&A section in the Discussion.