From 525b5cdb7c5d7c48e1ffa4af31d9d805045f6513 Mon Sep 17 00:00:00 2001 From: chris-krenz Date: Mon, 29 Apr 2024 23:26:39 -0400 Subject: [PATCH] fixed verilog template --- library/templates/cello_verilog_template.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/templates/cello_verilog_template.v b/library/templates/cello_verilog_template.v index 504239b..285917a 100644 --- a/library/templates/cello_verilog_template.v +++ b/library/templates/cello_verilog_template.v @@ -14,7 +14,7 @@ module and_gate (in_A, in_B, out); output out; - assign out = in_A & in_B; + and(out, in_A, in_B); endmodule