diff --git a/library/templates/cello_verilog_template.v b/library/templates/cello_verilog_template.v
index 504239b..285917a 100644
--- a/library/templates/cello_verilog_template.v
+++ b/library/templates/cello_verilog_template.v
@@ -14,7 +14,7 @@ module and_gate (in_A, in_B, out);
 
     output out;
 
-    assign out = in_A & in_B;
+    and(out, in_A, in_B);
 
 endmodule