diff --git a/configs/evb-ast2600-spl_defconfig b/configs/evb-ast2600-spl_defconfig
index 450387859c21..04c43fa81711 100644
--- a/configs/evb-ast2600-spl_defconfig
+++ b/configs/evb-ast2600-spl_defconfig
@@ -114,6 +114,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_NCSI=y
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 2ccf37d9c86a..ae15f35a9008 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -259,7 +259,7 @@ static int read_fsr(struct spi_nor *nor)
  * location. Return the configuration register value.
  * Returns negative if error occurred.
  */
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) || defined(CONFIG_SPI_FLASH_XMC)
 static int read_cr(struct spi_nor *nor)
 {
 	int ret;
@@ -1529,7 +1529,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
 }
 #endif
 
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) || defined(CONFIG_SPI_FLASH_XMC)
 /*
  * Write status Register and configuration register with 2 bytes
  * The first byte will be written to the status register, while the
@@ -2532,8 +2532,14 @@ static int spi_nor_init_params(struct spi_nor *nor,
 		}
 
 		/* need to disable hold/reset pin feature */
-		if (JEDEC_MFR(info) == SNOR_MFR_ST)
+#ifdef CONFIG_SPI_FLASH_STMICRO
+		if ((JEDEC_MFR(info) == SNOR_MFR_ST))
 			params->quad_enable = micron_read_cr_quad_enable;
+#endif
+
+#ifdef CONFIG_SPI_FLASH_XMC
+		params->quad_enable = winbond_sr2_bit1_quad_enable;
+#endif
 
 		if (JEDEC_MFR(info) == SNOR_MFR_GIGADEVICE)
 			params->quad_enable = winbond_sr2_bit1_quad_enable;
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 18338ec67b51..44cb236b9c1a 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -369,8 +369,13 @@ const struct flash_info spi_nor_ids[] = {
 #endif
 #ifdef CONFIG_SPI_FLASH_XMC
 	/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
-	{ INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+    { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+    { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ| SPI_NOR_4B_OPCODES) },
+    { INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ| SPI_NOR_4B_OPCODES) },
+    { INFO("XM25QH512C", 0x204020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ| SPI_NOR_4B_OPCODES) },
+    { INFO("XM25QU512C", 0x204120, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ| SPI_NOR_4B_OPCODES) },
 #endif
 	{ },
 };